MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 506

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Message Digest Hardware Accelerator (MDHA)
26.3.1
The MDHA Top Control block enables the FIFO whenever the MDHA module is enabled. This
block also captures both error and done status from the MDHA Logic block and generates a single
interrupt to the interrupt controller.
26.3.2
The FIFO block contains a 16 × 32-bit FIFO that is used for temporary storage of the data to be
hashed.
26.3.3
The MDHA logic block consists of 7 sub-blocks: the address decoder, interface control,
auto-padder, auto-padder control, algorithm engine, algorithm engine control, and status interrupt
as shown in
26.3.3.1 Address Decoder
The address decoder drives out the proper data from the module or captures incoming data into the
appropriate register.
26.3.3.2 Interface Control
The interface block decodes the MDMR and outputs all control signals to all other blocks. Control
signals are received from other modules to send a pop signal to the FIFO.
26.3.3.3 Auto-Padder
The Auto-padder takes longwords in from the FIFO and then either passes it directly to the engine
or pads the word according to the control bits that are set. The IPAD and OPAD is done to all
longwords in this block before they are passed directly to the engine. This block takes care of
passing the proper data to the engine for the EHMAC mode of operation. This is done by an
internal counter that will leave 351 bits in the Input FIFO.
26.3.3.4 Hashing Engine
This module is the core of the Message Digest Hardware Accelerator that is capable of computing
the Secure Hash Algorithm (SHA-1) or Message Digest 5 (MD5).
26-14
MDHA Top Control
FIFO
MDHA Logic
Figure
26-11.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor