MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 325

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Address
31–18
17–16
13–12
Reset
Reset
Bits
15
14
11
W
W
R
R RE
—
31
15
0
Name
CASL
Figure 18-3. DRAM Address and Control Registers (DACRn)
BA
RE
—
—
—
—
30
14
0
0
—
—
29
13
Base address register. With DCMR[BAM], determines the address range in which the
associated DRAM block is located. Each BA bit is compared with the corresponding address
of the current bus cycle. If all unmasked bits match, the address hits in the associated DRAM
block. BA functions the same as in asynchronous operation.
Reserved, should be cleared.
Refresh enable. Determines when the DRAM controller generates a refresh cycle to the
DRAM block.
0 Do not refresh associated DRAM block
1 Refresh associated DRAM block
Reserved, should be cleared.
CAS latency. Affects the following SDRAM timing specifications. Timing nomenclature varies
with manufacturers. Refer to the SDRAM specification for the appropriate timing
nomenclature:
Reserved, should be cleared.
CASL
t
assertion
t
t
t
t
command
t
RCD
CASL
RAS
RP
RWL
EP
—Precharge command to
—Last data out to precharge command
—
—
28
12
Table 18-5. DACRn Field Descriptions
—
—SD_SRAS assertion to SD_SCAS
,
—SD_SCAS assertion to data out
t
RDL
ACTV
—Last data input to precharge
IPSBAR+0x00_0048 (DACR0); 0x00_0050 (DACR1)
—
27
11
0
0
MCF5271 Reference Manual, Rev. 2
command to precharge command
—
—
26
10
Parameter
CBM
25
—
—
9
BA
ACTV
—
—
24
8
command
23
—
Description
0
0
7
IMRS
—
22
6
0
CASL=
00
—
—
1
1
2
1
1
1
21
5
PS
Number of Bus Clocks
—
—
20
4
CASL =
01
2
4
1
2
2
1
Memory Map/Register Definition
—
IP
—
19
3
CASL=
—
18
0
0
2
10
3
3
6
3
1
1
17
0
0
0
0
1
CASL=
11
3
3
6
3
1
1
16
0
0
0
0
0
18-7