MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 465

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

In either case, the data bits are loaded into the data portion of the FIFO while the A/D bit is loaded
into the status portion of the FIFO normally used for a parity error (USRn[PE]).
Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of
the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode may still
contain error detection and correction information. One way to provide error detection, if 8-bit
characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit
character.
24.4.5
This section describes bus operation during read, write, and interrupt acknowledge cycles to the
UART module.
24.4.5.1 Read Cycles
The UART module responds to reads with byte data. Reserved registers return zeros.
24.4.5.2 Write Cycles
The UART module accepts write data as bytes only. Write cycles to read-only or reserved registers
complete normally without exception processing, but data is ignored.
24.4.6
The software flowchart,
Freescale Semiconductor
• UART module initialization—These routines consist of SINIT and CHCHK (See
• I/O driver routine—This routine (See
• Interrupt handling—Consists of SIRQ (See
Figure 24-25
routine allocates 2 words on the system FIFO. On return to the calling routine, SINIT passes
UART status data on the FIFO. If SINIT finds no errors, the transmitter and receiver are
enabled. SINIT calls CHCHK to perform the checks. When called, SINIT places the UART
in local loop-back mode and checks for the following errors:
— Transmitter never ready
— Receiver never ready
— Parity error
— Incorrect character received
the terminal input character routine which gets a character from the receiver, and OUTCH,
which sends a character to the transmitter.
UART module generates an interrupt caused by a change-in-break (beginning of a break).
Bus Operation
Programming
and
Figure
Figure
24-25, consists of the following:
24-26). Before SINIT is called at system initialization, the calling
MCF5271 Reference Manual, Rev. 2
Figure 24-28
Figure
24-28), which is executed after the
and
Figure
24-29) consists of INCH,
Functional Description
24-27