MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 517

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

27.3
The RNG has three functional blocks. They are the Output FIFO, internal bus interface and the
RNG Core/Control Logic blocks, as shown in
blocks in more detail.
27.3.1 Output FIFO
The Output FIFO provides temporary storage for random data generated by the RNG Core/Control
Logic block. This allows the user to read multiple random long words back to back. The RNGSR,
allows the user to monitor the number of random words in the FIFO through the Output FIFO
Level field. If the user reads from the FIFO when it is empty and the interrupt is enabled, the RNG
will drive an interrupt request to the interrupt controller. It is very important that the user polls the
RNGSR[OFL] bit to make sure random values are present before reading from the FIFO.
27.3.2 RNG Core/Control Logic Block
This block contains the RNG’s control logic as well as its core engine used to generate random
data.
27.3.3 RNG Control Block
The Control Block contains the address decoder, all addressable registers, and control state
machines for the RNG. This block is responsible for communication with both the peripheral
interface and the FIFO interface. The block also controls the Core Engine to generate random data.
The general functionality of the block is as follows. After reset, entropy is generated and stored in
the RNG’s shift registers. After the GO Bit is set in the RNGCR, the FIFO is loaded with a random
word every 256 cycles. The process of loading the FIFO continues as long as the FIFO is not full.
Freescale Semiconductor
Functional Description
Output FIFO
RNG Core/Control
Logic
Figure 27-5. RNG Block Diagram
MCF5271 Reference Manual, Rev. 2
Figure
Random Number
Generator
27-5. The following sections describe these
Internal Bus
Internal
Control
Signals
Functional Description
27-5