MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 508

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Message Digest Hardware Accelerator (MDHA)
26.4.2.1 Generation of Key with IPAD
26.4.2.2 Generation of Key with OPAD
26-16
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, IPAD, and MD initialization.
4. The data FIFO is filled with the key.
5. MDDSR register write. Load this register with the length of the key (without padding) in
6. MDHA does the required IPAD of key.
7. MDHA does the required algorithm’s auto padding of message.
8. Set the MDCMR[GO] bit.
9. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful
10. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest and the
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, OPAD, and MD initialization.
4. The data FIFO is filled with the key.
5. MDDSR register write. Load this register with the length of the key (without padding) in
6. MDHA does the required OPAD of key.
7. MDHA does the required algorithm’s auto padding of message.
8. Set the MDCMR[GO] bit.
9. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful
bytes.
completion (or failure).
message digest count from the message digest registers.
bytes.
completion (or failure).
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message
data. This will most likely occur if the MDDSR write is not received
or auto-padding is disabled and a partial message block is provided.
MCF5271 Reference Manual, Rev. 2
NOTE
Freescale Semiconductor