MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 395

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 20
Watchdog Timer Module
20.1
The watchdog timer (WDT) is a 16-bit timer used to help software recover from runaway code.
The watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on
underflow. To prevent a reset, software must periodically restart the countdown by servicing the
watchdog.
20.1.1 Low-Power Mode Operation
This subsection describes the operation of the watchdog module in low-power modes and halted
mode of operation (by issuing a HALT instruction). Low-power modes are described in
“Power
modes, and shows how this module may facilitate exit from each mode.
In wait mode with the watchdog control register’s WAIT bit (WCR[WAIT]) set, watchdog timer
operation stops. In wait mode with the WCR[WAIT] bit cleared, the watchdog timer continues to
operate normally. In doze mode with the WCR[DOZE] bit set, the watchdog timer module
operation stops. In doze mode with the WCR[DOZE] bit cleared, the watchdog timer continues to
operate normally. Watchdog timer operation stops in stop mode. When stop mode is exited, the
watchdog timer continues to operate in its pre-stop mode state.
In halted mode (entered by issuing a HALT instruction) with the WCR[HALTED] bit set,
watchdog timer module operation stops. When halted mode is exited, watchdog timer operation
continues from the state it was in before entering halted mode, but any updates made in halted
mode remain. If the WCR[HALTED] bit is cleared, the watchdog timer continues to operate
normally after executing a HALT instruction. This is a debug feature available for the user
Freescale Semiconductor
Low-power Mode
Management.”
Introduction
Doze
Stop
Wait
Table 20-1. Watchdog Module Operation in Low-power Modes
Table 20-1
Normal if WCR[DOZE] cleared, stopped otherwise
Normal if WCR[WAIT] cleared, stopped otherwise
MCF5271 Reference Manual, Rev. 2
shows the watchdog module operation in the low-power
Watchdog Operation
Stopped
Upon Watchdog reset
Upon Watchdog reset
Mode Exit
No
Chapter 8,
20-1