MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 444

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

UART Modules
24-6
Bits
4–3
1–0
7
6
5
2
RxRTS
RxIRQ/
FFULL
Name
ERR
B/C
PM
PT
Address
Reset
W
R RXRTS RXIRQ/
Receiver request-to-send. Allows the UnRTS output to control the UnCTS input of the
transmitting device to prevent receiver overrun. If both the receiver and transmitter are
incorrectly programmed for UnRTS control, UnRTS control is disabled for both. Transmitter
RTS control is configured in UMR2n[TxRTS].
0 The receiver has no effect on UnRTS.
1 When a valid start bit is received, UnRTS is negated if the UART's FIFO is full. UnRTS is
Receiver interrupt select.
0 RxRDY is the source that generates interrupt or DMA requests.
1 FFULL is the source that generates interrupt or DMA requests.
Error mode. Configures the FIFO status bits, USRn[RB,FE,PE].
0 Character mode. The USRn values reflect the status of the character at the top of the FIFO.
1 Block mode. The USRn values are the logical OR of the status for all characters reaching
Parity mode. Selects the parity or multidrop mode for the channel. The parity bit is added to the
transmitted character, and the receiver performs a parity check on incoming data. The value of
PM affects PT, as shown below.
Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or
address character is transmitted (PM = 11).
Bits per character. Select the number of data bits per character to be sent. The values shown
do not include start, parity, or stop bits.
00 5 bits
01 6 bits
10 7 bits
11 8 bits
Figure 24-3. UART Mode Registers 1 (UMR1n)
reasserted when the FIFO has an empty position available.
ERR must be 0 for correct A/D flag information when in multidrop mode.
the top of the FIFO since the last
See
0
7
Table 24-3. UMR1n Field Descriptions
Section 24.3.5, “UART Command Registers
After UMR1n is read or written, the pointer points to UMR2n.
IPSBAR + 0x0200 (UART0); IPSBAR + 0x0240 (UART1);
PM
00
01
10
11
FFULL
MCF5271 Reference Manual, Rev. 2
0
6
With parity
Force parity
No parity
Multidrop mode
Parity Mode
ERR
0
5
IPSBAR + 0x0280 (UART2)
0
4
RESET ERROR STATUS
Even parity
Low parity
Data character
PM
Parity Type (PT= 0)
Description
0
3
PT
2
0
(UCRn).”
command for the channel was issued.
n/a
Address character
Odd parity
High parity
0
1
Parity Type (PT= 1)
B/C
0
0
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