MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 272

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DMA Controller Module
14.3.3 Destination Address Registers (DAR0–DAR3)
DARn, shown in
14.3.4 Byte Count Registers (BCR0–BCR3) and DMA Status
BCRn, shown in
BCRn decrements on the successful completion of the address transfer of a write transfer. BCRn
decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively.
14-8
Address
Address
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
Figure 14-6. Byte Count Registers (BCRn) and Status Registers (DSRn)
Registers (DSR0–DSR3)
31
15
31
15
0
0
0
0
The DMA does not maintain coherency with the cache. Therefore,
DMAs should not transfer data to cacheable memory unless software
is used to maintain the cache coherency.
Figure
Figure
30
14
30
14
0
0
0
0
Figure 14-5. Destination Address Registers (DARn)
29
13
29
13
0
0
0
0
14-6, contains the number of bytes yet to be transferred for a given block.
14-5, holds the address to which the DMA controller sends data.
28
12
28
12
IPSBAR + 0x00_0104 (DMA0); IPSBAR + 0x00_0114 (DMA1);
IPSBAR + 0x00_0108 (DMA0); IPSBAR + 0x00_0118 (DMA1);
0
0
0
0
IPSBAR + 0x00_0124 (DMA2); IPSBAR + 0x00_0134 (DMA3)
IPSBAR + 0x00_0128 (DMA2); IPSBAR + 0x00_0138 (DMA3)
DSR
27
27
11
11
0
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
26
10
0
0
0
0
25
25
0
0
0
0
9
9
NOTE
24
24
0
0
0
0
8
8
DAR
DAR
BCR
23
23
0
0
0
0
7
7
22
22
0
6
0
0
6
0
21
21
0
0
0
0
5
5
20
20
0
0
0
0
4
4
BCR
19
19
0
0
0
0
3
3
Freescale Semiconductor
18
18
0
0
0
0
2
2
17
17
0
0
0
0
1
1
16
16
0
0
0
0
0
0