MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 557

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

30.4.1 Revision A Shared Debug Resources
In the Revision A implementation of the debug module, certain hardware structures are shared
between BDM and breakpoint functionality as shown in
Thus, loading a register to perform a specific function that shares hardware resources is destructive
to the shared function. For example, a BDM command to access memory overwrites an address
breakpoint in ABHR. A BDM write command overwrites the data breakpoint in DBR.
30.4.2 Address Attribute Trigger Register (AATR)
The AATR, shown in
trigger. The register value is compared with address attribute signals from the processor’s local
high-speed bus, as defined by the setting of the trigger definition register (TDR). AATR is
accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and
through the BDM port using the
Freescale Semiconductor
DRc[4:0]
Reset
W RM
R
15
0
Register
Debug control registers can be written by the external development
system or the CPU through the WDEBUG instruction.
CSR is write-only from the programming model. It can be read or
written through the BDM port using the
commands.
ABHR
AATR
DBR
14
0
Figure 30-5. Address Attribute Trigger Register (AATR)
SZM
Table 30-5. Rev. A Shared BDM/Breakpoint Hardware
Bus attributes for all memory commands
Address for all memory commands
Data for all BDM write commands
13
Figure
0
12
0
TTM
30-5, defines address attributes and a mask to be matched in the
WDMREG
BDM Function
11
0
MCF5271 Reference Manual, Rev. 2
10
0
command.
TMM
0
9
NOTE
0
8
0x06
R
0
7
Table
Data for data breakpoint
Attributes for address breakpoint
Address for address breakpoint
RDMREG
0
6
SZ
Breakpoint Function
30-5.
0
5
and
0
4
TT
Memory Map/Register Definition
WDMREG
0
3
1
2
TM
1
0
1
0
30-7