MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 529

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

28.2.1.5 SKHA Error Status Register (SKESR)
The read-only SKESR indicates the type of error that has occurred. These errors are described
below and shown in
interrupt request to the interrupt controller. If multiple errors occur, only the first error will be
flagged. The SKHA must be reset when any error occurs. A write to this register has no effect.
Freescale Semiconductor
Address
Reset
Reset
Bits
4
3
2
1
0
W
W
R
R
31
15
0
0
0
0
DONE
Name
BUSY
ERR
INT
RD
30
14
0
0
0
0
Figure 28-12. SKHA Error Status Register (SKESR)
Table
Table 28-5. SKSR Field Descriptions (Continued)
29
13
0
0
0
0
Busy. Indicates the SKHA is busy. Mode, key data, context, and key size registers may not
be modified and context registers may not be read while busy.
0 SKHA idle
1 SKHA busy
Reset done. Indicates if reset of the SKHA module has completed.
0 Reset in progress
1 Reset complete
Error interrupt. Indicates that an error has occurred.
0 No error
1 Error occurred
Done interrupt. Indicates that the module has finished processing.
0 Not done
1 Done processing
SKHA interrupt. Indicates that the module has finished processing data and the result is
ready to be read from the Output FIFO or there is an error. This bit will assert when an
interrupt request in generated unless the SKHACR[IE] bit is not set.
0 No interrupt
1 Done or error interrupt
28-6. When an error occurs, the SKHA engine will halt and assert an
28
12
0
0
0
0
MCF5271 Reference Manual, Rev. 2
27
11
0
0
0
0
KRE KPE ERE RMDP KSE DS
26
10
0
0
0
IPSBAR + 0x1B_0010
25
0
0
0
9
24
0
0
0
8
Description
23
0
0
0
7
22
0
0
0
6
21
E
0
0
0
5
IME NEOF NEIF OFU IFO
20
0
0
0
4
Memory Map/Register Definition
19
0
0
0
3
18
0
0
0
2
17
0
0
0
1
16
0
0
0
0
28-11