MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 563

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

30.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)
The PBR defines an instruction address for use as part of the trigger. This register’s contents are
compared with the processor’s program counter register when TDR is configured appropriately.
PBR bits are masked by setting corresponding PBMR bits. Results are compared with the
processor’s program counter register, as defined in TDR.
register.
The PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and
through the BDM port using the
Section 30.5.3.3, “Command Set
Freescale Semiconductor
DRc[4:0]
Reset
Reset
31–0
Bits
W
W
R
R
—
—
31
15
Address
Name
Figure 30-9. Program Counter Breakpoint Register (PBR)
—
—
30
14
Table 30-12. Access Size and Operand Data Location
29
—
13
—
PC breakpoint address. The 32-bit address to be compared with the PC as a breakpoint
trigger.
—
—
28
12
Table 30-13. PBR Field Descriptions
A[1:0]
00
01
10
11
0x
1x
xx
27
—
—
11
Descriptions.”
MCF5271 Reference Manual, Rev. 2
RDMREG
—
—
26
10
Access Size
Longword
—
—
25
9
Word
Word
Byte
Byte
Byte
Byte
Program Counter
Program Counter
and
—
—
24
8
0x08
WDMREG
—
—
23
Description
7
Operand Location
Figure 30-9
—
—
22
6
D[31:24]
D[23:16]
D[31:16]
D[15:8]
D[15:0]
D[31:0]
commands using values shown in
D[7:0]
—
—
21
5
20
—
—
4
shows the PC breakpoint
Memory Map/Register Definition
—
—
19
3
18
—
—
2
—
—
17
1
—
—
16
0
30-13