MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 46

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Overview
1.3.7
The MCF5271 contains three full-duplex UARTs that function independently. The three UARTs
can be clocked by the system bus clock, eliminating the need for an externally supplied clock.
They can use DMA requests on transmit-ready and receive-ready as well as interrupt requests for
servicing. Flow control via UnCTS and UnRTS pins is provided on all three UARTS.
1.3.8
The I
exchange, minimizing the interconnection between devices. This bus is suitable for applications
requiring occasional communications over a short distance between many devices.
1.3.9
The queued serial peripheral interface module provides a high-speed synchronous serial peripheral
interface with queued transfer capability. It allows up to 16 transfers to be queued at once,
eliminating CPU intervention between transfers.
1.3.10 Cryptography
The superset device, MCF5271, incorporates small, fast, dedicated hardware accelerators for
random number generation, message digest and hashing, and the DES, 3DES, and AES block
cipher functions allowing for the implementation of common Internet security protocol
cryptography operations with performance well in excess of software-only algorithms.
1.3.11 DMA Timers (DTIM0-DTIM3)
There are four independent, DMA-transfer-generating 32-bit timers (DTIM[3:0]) on the
MCF5271. Each timer module incorporates a 32-bit timer with a separate register set for
configuration and control. The timers can be configured to operate from the system clock or from
an external clock source using one of the DTINn signals. If the system clock is selected, it can be
divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler
which clocks the actual timer counter register (TCRn). Each of these timers can be configured for
input capture or reference compare mode. By configuring the internal registers, each timer may be
configured to assert an external signal, generate an interrupt on a particular event or cause a DMA
transfer.
1.3.12 Periodic Interrupt Timers (PIT0-PIT3)
The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at
regular intervals with minimal processor intervention. Each timer can either count down from the
value written in its PIT modulus register, or it can be a free-running down-counter.
1-10
2
C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
UARTs
I
QSPI
2
C Bus
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor