MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 139

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7.1.3.1
In normal mode with a crystal reference, the PLL receives an input clock frequency from the
crystal oscillator circuit and multiplies the frequency to create the PLL output clock. It can
synthesize frequencies ranging from 4x to 18x the reference frequency and has a post divider
capable of reducing this synthesized frequency without disturbing the PLL. The user must supply
a crystal oscillator that is within the appropriate input frequency range, the crystal manufacture’s
recommended external support circuitry, and short signal route from the device to the crystal. In
normal mode, the PLL can generate a frequency modulated clock or a non-modulated clock
(locked on a single frequency). The modulation rate, modulation depth, output clock divide ratio
(RFD), and whether the PLL is modulating or not can be programmed by writing to the PLL
registers through the bus interface.
7.1.3.2
Same as
by an external clock generator rather than a crystal oscillator. However, the input frequency range
is the same as the crystal reference. To enter normal mode with external clock Generator reference,
the PLL configuration must be set by following the procedure outlined in
Clock Generation.”
7.1.3.3
When 1:1 PLL mode is selected, the PLL synthesizes a core clock frequency equal to two times
the input reference frequency (f
frequency modulation capability is not available. Further, modulation must not be present on the
input reference clock. The input reference frequency is an external clock reference from a master
MCU CLKOUT pin or other external clock generator source. To enter 1:1 PLL mode, the PLL
must be set by following the procedure outlined in
7.1.3.4
During external clock mode, the PLL is completely bypassed and the user must supply an external
clock on the EXTAL pin. The external clock is used directly to produce the internal core clocks.
Refer to the Hardware Specification document for external clock input requirements. In external
clock mode, the analog portion of the PLL is disabled and no clocks are generated at the PLL
Freescale Semiconductor
Section 7.1.3.1, “Normal PLL Mode with Crystal Reference,”
Normal PLL Mode with Crystal Reference
Normal PLL Mode with External Reference
1:1 PLL Mode
External Clock Mode (Bypass Mode)
When configured for 1:1 PLL mode, it is imperative that the
CLKOUT clock divider not be changed from its reset state of
divide-by-2. Increasing or decreasing this divide ratio will produce
unpredictable results from the PLL.
sys
MCF5271 Reference Manual, Rev. 2
=2×f
ref
and f
NOTE
sys/2
Section 7.4.3, “System Clock Generation.”
=f
ref
) The post divider is not active and the
except EXTAL is driven
Section 7.4.3, “System
Introduction
7-5