MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 215

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

At reset, these on-chip modules are configured to have only supervisor read/write access
capabilities. If an instruction fetch access to any of these peripheral modules is attempted, the IPS
bus cycle is immediately terminated with an error.
11.4.3.3 Grouped Peripheral Access Control Register (GPACR)
The on-chip peripheral space starting at IPSBAR is subdivided into sixteen 64-Mbyte regions. The
first region has a unique access control register associated with it. The other fifteen regions are in
reserved space; the access control registers for these regions are not implemented. The access
control register is 8 bits in width so that read, write, and execute attributes may be assigned to the
given IPS region.
Freescale Semiconductor
Bits
6–4
3–0
7
Table 11-11. Peripheral Access Control Registers (PACRn) (Continued)
Figure 11-10. Grouped Peripheral Access Control Register (GPACR)
The access control for modules with memory space protected by
PACR0–PACR8 are determined by the PACR0–PACR8 settings. The
access control is not affected by GPACR, even though the modules are
mapped in its 64-Mbyte address space.
ACCESS_
Name
LOCK
CTRL
IPSBAR Offset
Address
—
Reset
0x02D
0x02E
W
R LOCK
This bit, once set, prevents subsequent writes to the GPACR. Any attempted write to the
GPACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
Reserved, should be cleared.
This 4-bit field defines the access control for the given memory region.
The encodings for this field are shown in
Table 11-12. (GPACR) Field Descriptions
0
7
MCF5271 Reference Manual, Rev. 2
0
0
6
PACR8
Name
—
0
0
5
NOTE
IPSBAR + 0x030
0
0
4
ACCESS_CTRL1
FEC0
Description
—
0
3
Modules Controlled
Table
ACCESS_CTRL
11-13.
2
0
ACCESS_CTRL0
0
1
System Access Control Unit (SACU)
—
—
0
0
11-17