MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 297

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

16.4.1 Chip Select Module Registers
The chip select module is programmed through the chip select address registers
(CSAR0–CSAR7), chip select mask registers (CSMR0–CSMR7), and the chip select control
registers (CSCR0–CSCR7).
16.4.1.1 Chip Select Address Registers (CSAR0–CSAR7)
The CSARs,
Freescale Semiconductor
1
0x00_00C0
0x00_00C4
0x00_00C8
0x00_00D0
0x00_00D4
0x00_00D8
0x00_00A0
0x00_00A4
0x00_00A8
0x00_00B0
0x00_00B4
0x00_00B8
0x00_00C
0x00_00D
0x00_00A
0x00_00B
IPSBAR
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these
reserved address spaces and reserved register bits have no effect.
Offset
C
C
C
C
Figure
Chip select address register—bank 3 (CSAR3)
Chip select address register—bank 4 (CSAR4)
Chip select address register—bank 5 (CSAR5)
Chip select address register—bank 6 (CSAR6)
Chip-select address register—bank 7 (CSAR7)
[31:24]
16-4, specify the chip select base addresses.
Table 16-4. Chip Select Registers (Continued)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MCF5271 Reference Manual, Rev. 2
Chip select mask register—bank 3 (CSMR3)
Chip select mask register—bank 4 (CSMR4)
Chip-select mask register—bank 7 (CSMR7)
1
1
1
Chip select mask register—bank 5 (CSMR5)
1
Chip select mask register—bank 6 (CSMR6)
1
1
[23:16]
Chip-select control register—bank 7 (CSCR7)
Chip select control register—bank 2 (CSCR2)
Chip select control register—bank 3 (CSCR3)
Chip select control register—bank 4 (CSCR4)
Chip select control register—bank 5 (CSCR5)
Chip select control register—bank 6 (CSCR6)
[15:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Memory Map/Register Definition
1
1
1
1
1
[7:0]
16-7