MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 207

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

the two writes. If the CWT has already timed out, writing to this register has no effect in negating
the CWT interrupt.
uninitialized.
11.3 Internal Bus Arbitration
The internal bus arbitration is performed by the on-chip bus arbiter, which containing the
arbitration logic that controls which of up to four MBus masters (M0–M3 in
access to the external buses. The function of the arbitration logic is described in this section.
11.3.1 Overview
The basic functionality is that of a 4-port, pipelined internal bus arbitration module with the
following attributes:
Freescale Semiconductor
Address
Figure 11-5. Core Watchdog Service Register (CWSR)
Reset
Figure 11-5
W
R
DMA
CPU
FEC
—
7
Figure 11-6. Arbiter Module Functions
M3
SRAM1
M0
M2
illustrates the CWSR. At system reset, the contents of CWSR are
—
MCF5271 Reference Manual, Rev. 2
6
“back door” to SRAM
MARB
—
5
MPARK
IPSBAR + 0x013
—
CWSR[7:0]
4
—
3
Modules
Internal
SDRAMC
EIM
RAMBAR
—
2
—
1
—
0
Internal Bus Arbitration
Figure
11-6) has
11-9