MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 535

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

28.3.1 Transmit FIFO Interface Block
This block translates the internal FIFO control signals to the input FIFO and passes the message
data to the SKHA logic block. The SKHA logic block will continue to pop data from the input
FIFO until the FIFO is empty.
For AES, four 32-bit words are required to process a block. For DES/3DES, two 32-bit words are
required to process a block.
28.3.2 Receive FIFO Interface Block
This block translates the internal FIFO control signals to the output FIFO and pass the processed
message data from the SKHA logic block. The SKHA logic block will push the same number of
words to the output FIFO as it pops from the input FIFO. The SKHA logic block will push to the
output FIFO as long as the FIFO is not full. Once the last word is pushed to the output FIFO, the
done interrupt will be asserted.
28.3.3 Top Control Block
This block generates the input and output FIFO transmit, receive and request signals and translates
other internal signals at the top level.
28.3.4 SKHA Logic Block
This block contains the internal address decoder, addressable registers (key data, key size, data
size, mode, context data, and status), interrupt and error logic, and the core engine as shown in
Figure
Freescale Semiconductor
.
28-16.
Figure 28-16. SKHA Logic Block Diagram
Decoder
Address
MCF5271 Reference Manual, Rev. 2
Register
Registers
Mode
Key
Data Size
Register
Key Size
Register
SKHA
Core
Register
Status
Error Status
Block
SKHA LOGIC
Out Block
In Block
Functional Description
28-17