MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 244

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
General Purpose I/O Module
12.3.1.7.2 FEC/I2C Drive Strength Control Register (DSCR_FECI2C)
The DSCR_FECI2C register controls the output drive strengths of the following pins: EMDC,
EMDIO, I2C_SDA, and I2C_SCL.
12-28
Bits
7–5
3–1
4
0
Figure 12-39. External Bus Drive Strength Control Register (DSCR_EIM)
Figure 12-40. FEC/I2C Drive Strength Control Register (DSCR_FECI2C)
DSCR_EIM1 EIM function drive strength 1. This bit sets the drive strength on the following pins:
DSCR_EIM0 EIM function drive strength 0. The DSCR_EIM0 bit sets the drive strength on the
Address
Address
Name
Reset
Reset
W
W
R
R
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Table 12-18. DSCR_EIM Field Descriptions
0
0
0
0
7
7
Reserved, should be cleared.
A[23:0], D[31:0], BS[3:0], OE, R/W, CS[7:0], SD_SCAS, SD_SRAS, SD_WE, SCKE,
SD_CS[1:0], and RSTOUT.
0 Pins set at low drive
1 Pins set at high drive
Reserved, should be cleared.
following pins: TA, TEA, TIP, TS, and TSIZ[1:0].
0 Pins set at low drive
1 Pins set at high drive
0
0
0
0
6
6
MCF5271 Reference Manual, Rev. 2
0
0
0
0
5
5
IPSBAR + 0x10_0050
IPSBAR + 0x10_0052
See Note
See Note
DSCR_
DSCR_
EIM1
FEC
4
4
Description
0
0
0
0
3
3
2
0
0
2
0
0
0
0
0
0
1
1
See Note
See Note
DSCR_
DSCR_
EIM0
I2C
0
0
Freescale Semiconductor

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