MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 436

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Queued Serial Peripheral Interface (QSPI) Module
23.3.8 Programming Example
The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of
4.688 MHz. The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are
used in this example.
23-16
1. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the falling
2. Write QDLYR with the desired delays.
3. Write QIR with 0xD00F to enable write collision, abort bus errors, and clear any
4. Write QAR with 0x0020 to select the first command RAM entry.
clock edge, and a QSPI_CLK frequency of 4.688 MHz (assuming a 75-MHz internal bus
clock).
interrupts.
QS1: QSPI_CS to QSPI_CLK
QS2: QSPI_CLK to QSPI_DOUT VALID
QS3: QSPI_CLK to QSPI_DOUT HOLD
QS4: QSPI_DIN to QSPI_CLK SETUP
QS5: QSPI_DIN to QSPI_CLK HOLD
QSPI_CS[3:0]
QSPI_CLK
QSPI_DOUT
QSPI_DIN
1 T1 is defined as the clock period in ns.
QS1
QS2
QS3
MCF5271 Reference Manual, Rev. 2
Figure 23-11. QSPI Timing
10 ns
10 ns
0 ns
Min
1T1
QS4
20 ns
Max
QS5
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