MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 555

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Another example of a variant branch instruction would be a JMP (A0) instruction.
shows the PST and DDATA outputs that indicate a JMP (A0) execution (assuming the CSR was
programmed to display the lower 2 bytes of an address).
PST 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the
subsequent 4 nibbles of DDATA display the lower 2 bytes of address register A0 in
least-to-most-significant nibble order. The PST output after the JMP instruction completes
depends on the target instruction. The PST can continue with the next instruction before the
address has completely displayed on DDATA because of the DDATA FIFO. If the FIFO is full and
the next instruction has captured values to display on DDATA, the pipeline stalls (PST = 0x0) until
space is available in the FIFO.
30.4
In addition to the existing BDM commands that provide access to the processor’s registers and the
memory subsystem, the debug module contains 19 registers to support the required functionality.
These registers are also accessible from the processor’s supervisor programming model by
executing the WDEBUG instruction (write only). Thus, the breakpoint hardware in the debug
module can be written by the external development system using the debug serial interface or by
the operating system running on the processor core. Software is responsible for guaranteeing that
accesses to these resources are serialized and logically consistent. Hardware provides a locking
mechanism in the CSR to allow the external development system to disable any attempted writes
by the processor to the breakpoint registers (setting CSR[IPW]). BDM commands must not be
issued if the MCF5271 is using the WDEBUG instruction to access debug module registers or the
resulting behavior is undefined.
These registers, shown in
implemented bits.
Freescale Semiconductor
3. The new target address is optionally available on subsequent cycles using the DDATA
PSTCLK
DDATA
port. The number of bytes of the target address displayed on this port is configurable (2, 3,
or 4 bytes).
PST
Memory Map/Register Definition
Figure 30-3. Example JMP Instruction Output on PST/DDATA
0x5
0x0
Figure
30-4, are treated as 32-bit quantities, regardless of the number of
0x9
0x0
MCF5271 Reference Manual, Rev. 2
default
A[3:0]
default
A[7:4]
A[11:8]
default
Memory Map/Register Definition
A[15:12]
default
Figure 30-3
30-5