MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 559

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

transfer on the processor’s high-speed local bus. The trigger definition register (TDR) identifies
the trigger as one of three cases:
ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG
instruction and via the BDM port using the
in supervisor mode as debug control register 0x0D using the WDEBUG instruction and via the
BDM port using the
30.4.4 Configuration/Status Register (CSR)
The CSR defines the debug configuration for the processor and memory subsystem and contains
status information from the breakpoint logic. CSR is write-only from the programming model. It
can be read from and written to through the BDM port. CSR is accessible in supervisor mode as
debug control register 0x00 using the WDEBUG instruction and through the BDM port using the
RDMREG
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1. Identical to the value in ABLR
2. Inside the range bound by ABLR and ABHR inclusive
3. Outside that same range
DRc[4:0]
Reset
Reset
31–0
31–0
Bits
Bits
W
W
R
R
and
—
—
31
15
WDMREG
Address
Address
Name
Name
Figure 30-6. Address Breakpoint Registers (ABLR, ABHR)
—
—
30
14
WDMREG
29
—
13
—
commands.
Low address. Holds the 32-bit address marking the lower bound of the address breakpoint
range. Breakpoints for specific addresses are programmed into ABLR.
High address. Holds the 32-bit address marking the upper bound of the address
breakpoint range.
—
—
28
12
Table 30-8. ABHR Field Description
Table 30-7. ABLR Field Description
command.
27
—
—
11
MCF5271 Reference Manual, Rev. 2
—
—
26
10
0x0D (ABLR); 0x0C (ABHR)
RDMREG
—
—
25
9
—
—
24
Address
Address
8
and
—
—
23
Description
Description
7
WDMREG
—
—
22
6
—
—
21
5
commands. ABLR is accessible
20
—
—
4
Memory Map/Register Definition
—
—
19
3
18
—
—
2
—
—
17
1
—
—
16
0
30-9