MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 24

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

28.2.1.12
28.3
28.3.1
28.3.2
28.3.3
28.3.4
28.3.4.1
28.3.4.2
28.3.4.3
28.3.5
28.4
28.4.1
28.4.2
29.1
29.1.1
29.1.2
29.1.3
29.2
29.2.1
29.2.2
29.2.3
29.2.4
29.2.5
29.2.6
29.3
29.3.1
29.3.1.1
29.3.1.2
29.3.1.3
29.3.1.4
29.3.1.5
29.4
29.4.1
29.4.2
29.4.3
29.4.3.1
29.4.3.2
xxiv
Paragraph
Number
Functional Description................................................................................................ 28-16
Initialization/Application Information ........................................................................ 28-19
Introduction................................................................................................................... 29-1
External Signal Description .......................................................................................... 29-3
Memory Map/Register Definition ................................................................................ 29-5
Functional Description.................................................................................................. 29-7
Transmit FIFO Interface Block............................................................................... 28-17
Receive FIFO Interface Block ................................................................................ 28-17
Top Control Block .................................................................................................. 28-17
SKHA Logic Block................................................................................................. 28-17
Security Assurance Features................................................................................... 28-19
General Operation................................................................................................... 28-19
Operation with Context Switch............................................................................... 28-20
Block Diagram.......................................................................................................... 29-1
Features..................................................................................................................... 29-2
Modes of Operation .................................................................................................. 29-3
JTAG Enable (JTAG_EN)........................................................................................ 29-3
Test Clock Input (TCLK) ......................................................................................... 29-4
Test Mode Select/Breakpoint (TMS/BKPT) ............................................................ 29-4
Test Data Input/Development Serial Input (TDI/DSI) ............................................. 29-4
Test Reset/Development Serial Clock (TRST/DSCLK) .......................................... 29-4
Test Data Output/Development Serial Output (TDO/DSO)..................................... 29-5
Register Descriptions................................................................................................ 29-5
JTAG Module ........................................................................................................... 29-7
TAP Controller ......................................................................................................... 29-7
JTAG Instructions..................................................................................................... 29-8
Address Decode Logic........................................................................................ 28-18
Error Interrupt/Status Logic................................................................................ 28-18
SKHA Core......................................................................................................... 28-18
Instruction Shift Register (IR) .............................................................................. 29-5
IDCODE Register................................................................................................. 29-5
Bypass Register .................................................................................................... 29-6
TEST_CTRL Register .......................................................................................... 29-6
Boundary Scan Register ....................................................................................... 29-6
EXTEST Instruction ............................................................................................. 29-9
IDCODE Instruction............................................................................................. 29-9
SKHA Context Registers (SKCRn)................................................................... 28-15
IEEE 1149.1 Test Access Port (JTAG)
MCF5271 Reference Manual, Rev. 2
Contents
Chapter 29
Title
Freescale Semiconductor
Number
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