MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 423

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

23.1.4 Internal Bus Interface
Because the QSPI module only operates in master mode, the master bit in the QSPI mode register,
QMR[MSTR], must be set for the QSPI to function properly. The QSPI can initiate serial transfers
but cannot respond to transfers initiated by other QSPI masters.
23.2 Operation
The QSPI uses a dedicated 80-Byte block of static RAM accessible both to the module and the
CPU to perform queued operations. The RAM is divided into three segments as follows:
The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word
of receive data comprise 1 of the 16 queue entries (0x0–0xF).
The user initiates QSPI operation by loading a queue of commands in command RAM, writing
transmit data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the
queued commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to
signal their completion. As another option, QIR[SPIFE] can be enabled to generate an interrupt.
The QSPI uses four queue pointers. The user can access three of them through fields in QSPI wrap
register (QWR):
Freescale Semiconductor
• 16 command control bytes (command RAM)
• 16 transmit data words (transfer RAM)
• 16 receive data words (transfer RAM)
• The new queue pointer, QWR[NEWQP], points to the first command in the queue.
• An internal queue pointer points to the command currently being executed.
• The completed queue pointer, QWR[CPTQP], points to the last command executed.
• The end queue pointer, QWR[ENDQP], points to the final command in the queue.
Serial Clock (QSPI_CLK)
Peripheral Chip Selects (QSPI_CS[3:0])
Table 23-1. QSPI Input and Output Signals and Functions (Continued)
Throughout ColdFire documentation, “word” is used consistently and
exclusively to designate a 16-bit data unit. The only exceptions to this
appear in discussions of serial communication modules such as QSPI
that support variable-length data units. To simplify these discussions
the functional unit is referred to as a ‘word’ regardless of length.
Signal Name
MCF5271 Reference Manual, Rev. 2
Actively driven
Actively driven
Hi-Z or Actively Driven
NOTE
Clock output from QSPI
Peripheral selects
Function
Operation
23-3