MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 293

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

16.3 Chip Select Operation
Each chip select has a dedicated set of registers for configuration and control.
CS0 is a global chip select after reset and provides relocatable boot ROM capability.
16.3.1 General Chip Select Operation
When a bus cycle is initiated, the MCF5271 first compares its address with the base address and
mask configurations programmed for chip selects 0–7 (configured in CSCR0–CSCR7) and
DRAM blocks 0 and 1 (configured in DACR0 and DACR1). If the driven address matches a
programmed chip select or DRAM block, the appropriate chip select is asserted or the DRAM
block is selected using the specifications programmed in the respective configuration register.
Otherwise, the following occurs:
Freescale Semiconductor
• Chip select address registers (CSARn) control the base address of the chip select. See
• Chip select mask registers (CSMRn) provide 16-bit address masking and access control.
• Chip select control registers (CSCRn) provide port size and burst capability indication,
• If the address and attributes do not match in CSAR or DACR, the MCF5271 runs an
• Should an address and attribute match in multiple CSCRs, the matching chip select signals
• If the address and attribute match both DACRs or a DACR and a CSAR, the operation is
Section 16.4.1.1.
See Section 16.4.1.2.
wait-state generation, and automatic acknowledge generation features. See
Section 16.4.1.3.
external burst-inhibited bus cycle with a default of external termination on a 32-bit port.
are driven; however, the chip select signals are driven during an external burst-inhibited bus
cycle with external termination on a 32-bit port.
undefined.
Table 16-1. Byte Enables/Byte Write Enable Signal Settings (Continued)
Transfer Size
Line
Port Size
16-bit
32-bit
8-bit
MCF5271 Reference Manual, Rev. 2
A1
0
0
1
1
0
1
0
A0
0
1
0
1
0
0
0
D[31:24]
BS3
0
0
0
0
0
0
0
D[23:16]
BS2
1
1
1
1
0
0
0
D[15:8]
BS1
1
1
1
1
1
1
0
D[7:0]
Chip Select Operation
BS0
1
1
1
1
1
1
0
16-3