MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 170

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Power Management
8.3.1.5
Most peripherals may be disabled by software in order to cease internal clock generation and
remain in a static state. Each peripheral has its own specific disabling sequence (refer to each
peripheral description for further details). A peripheral may be disabled at any time and will
remain disabled during any low-power mode of operation.
8.3.2
8.3.2.1
The ColdFire core is disabled during any low-power mode. No recovery time is required when
exiting any low-power mode.
8.3.2.2
SRAM is disabled during any low-power mode. No recovery time is required when exiting any
low-power mode.
8.3.2.3
The SCM’s core watchdog timer can bring the device out of all low-power modes except stop
mode. In stop mode, all clocks stop, and the core watchdog does not operate.
When enabled, the core watchdog can bring the device out of low-power mode via a core
watchdog interrupt. This system setup must meet the conditions specified in
“Low-Power
8.3.2.4
SDRAM Controller operation is unaffected by either the wait or doze modes; however, the
SDRAMC is disabled by stop mode. Since all clocks to the SDRAMC are disabled by stop mode,
the SDRAMC will not generate refresh cycles.
To prevent loss of data the SDRAMC should be placed in self-refresh mode by setting DCR[IS]
before entering stop mode. The SDRAM self-refresh mode allows the SDRAM to enter a
low-power state where internal refresh operations are used to maintain the integrity of the data
stored in the SDRAM.
8-6
Peripheral Behavior in Low-Power Modes
Peripheral Shut Down
ColdFire Core
Static Random-Access Memory (SRAM)
System Control Module (SCM)
SDRAM Controller (SDRAMC)
Modes” for the core watchdog interrupt to bring the part out of low-power mode.
Entering stop mode will disable the SDRAMC including the refresh
counter. If SDRAM is used, then code is required to insure proper
entry and exit from stop mode. See
Controller
(SDRAMC)” for more information.
MCF5271 Reference Manual, Rev. 2
NOTE
Section 8.3.2.4, “SDRAM
Freescale Semiconductor
Section 8.3.1,