MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 623

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

SKHA
SRAM
Stack pointer 3-3
System clock 7-15
T
TAP controller 29-7
Timers
Freescale Semiconductor
reset controller
SDRAM controller
summary 2-3
FIFO 28-14
logic 28-17
memory map 28-6
operation
registers
cache, interaction 5-3
initialization 6-4
operation
power management 6-5
registers
DTIM
RESET 10-2
RSTOUT 10-2
summary 18-4
AES 28-3
CBC 28-4
context switch 28-20
CTR 28-5
DES, 3DES 28-1
ECB 28-3
general 28-19
command (SKCMR) 28-9
context (SKCRn) 28-15
control (SKCR) 28-8
data size (SKDSR) 28-13
error status (SKESR) 28-11
error status mask (SKESMR) 28-12
key data (SKKDRn) 28-14
key size (SKKSR) 28-13
mode (SKMR) 28-7
status (SKSR) 28-10
low-power modes 8-6
RAMBAR 6-2
capture mode 22-3
code example 22-10
memory map 22-3
operation
output mode 22-3
prescaler 22-2
reference compare 22-3
registers
general 22-9
capture (DTCRn) 22-8
,
28-17
,
3-7
MCF5271 Reference Manual, Rev. 2
U
UART modules
PIT
WDT
clock select registers (UCSRn) 24-10
clock source
command registers (UCRn) 24-10
core interrupts 24-28
DMA service 24-28
FIFO stack 24-23
initialization 24-30
input port change (UIPCRn) 24-13
memory map 24-4
operation
registers
time-out values 22-11
block diagram 21-1
interrupts 21-7
memory map 21-2
operation
registers
timeout 21-7
memory map 20-2
operation
registers
baud rates 24-18
divider 24-17
external 24-19
looping modes
low-power modes 8-7
multidrop mode 24-25
receiver 24-21
transmitter 24-19
auxiliary control (UACRn) 24-13
baud rate generator (UBG1n/UBG2n) 24-15
counters (DTCNn) 22-8
event (DTERn) 22-6
mode (DTMRn) 22-4
reference (DTRRn) 22-7
free-running 21-6
low-power modes 8-10
set-and-forget 21-6
control and status (PCSR) 21-3
count (PCNTR) 21-5
modulus (PMR) 21-5
low-power 8-10
control (WCR) 20-3
count (WCNTR) 20-4
modulus (WMR) 20-4
service (WSR) 20-4
automatic echo 24-24
local loop-back 24-24
remote loop-back 24-25
,
20-1
,
21-2
Index-9