MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 386

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.3.9 Hash Algorithm
The hash table algorithm used in the group and individual hash filtering operates as follows. The
48-bit destination address is mapped into one of 64 bits, which are represented by 64 bits stored
in GAUR, GALR (group address hash match) or IAUR, IALR (individual address hash match).
This mapping is performed by passing the 48-bit address through the on-chip 32-bit CRC
generator and selecting the 6 most significant bits of the CRC-encoded result to generate a number
between 0 and 63. The msb of the CRC result selects GAUR (msb = 1) or GALR (msb = 0). The
least significant 5 bits of the hash result select the bit within the selected register. If the CRC
generator selects a bit that is set in the hash table, the frame is accepted; otherwise, it is rejected.
For example, if eight group addresses are stored in the hash table and random group addresses are
received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from
reaching memory. Those that do reach memory must be further filtered by the processor to
determine if they truly contain one of the eight desired addresses.
The effectiveness of the hash table declines as the number of addresses increases.
19-42
I/G - Individual/Group bit in Destination Address (least significant bit in first byte received in MAC frame)
NOTES:
FCE - field in RCR register (Flow Control Enable)
Figure 19-28. Ethernet Address Recognition—Microcode Decisions
Flush from FIFO
Hash Search
Group Table
Reject Frame
False
FCE
Match
False
?
?
False
True
True
Receive Frame
Pause Address
MCF5271 Reference Manual, Rev. 2
?
Group
Receive Frame
True
Receive Address
Recognition
I/G Address
Receive Frame
?
True
Individual Table
Flush from FIFO
Individual
Hash Search
Reject Frame
Match
False
?
False
Exact Match
?
Freescale Semiconductor
Receive Frame
True