MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 561

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
12–11
Bits
9–8
3–0
13
10
7
6
5
4
Name
EMU
DDC
SSM
UHE
BTB
NPL
IPI
—
—
Table 30-9. CSR Field Descriptions (Continued)
Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See
Section 30.6.1.1, “Emulator
Debug data control. Controls operand data capture for DDATA, which displays the number
of bytes defined by the operand reference size before the actual data; byte displays 8 bits,
word displays 16 bits, and long displays 32 bits (one nibble at a time across multiple
PSTCLK cycles). See
00 No operand data is displayed.
01 Capture all write data.
10 Capture all read data.
11 Capture all read and write data.
User halt enable. Selects the CPU privilege level required to execute the HALT instruction.
0 HALT is a supervisor-only instruction.
1 HALT is a supervisor/user instruction.
Branch target bytes. Defines the number of bytes of branch target address DDATA
displays.
00 0 bytes
01 Lower 2 bytes of the target address
10 Lower 3 bytes of the target address
11 Entire 4-byte target address
See
Reserved, should be cleared.
Non-pipelined mode. Determines whether the core operates in pipelined or mode or not.
0 Pipelined mode
1 Nonpipelined mode. The processor effectively executes one instruction at a time with
Regardless of the NPL state, a triggered PC breakpoint is always reported before the
triggering instruction executes. In normal pipeline operation, the occurrence of an address
and/or data breakpoint trigger is imprecise. In non-pipeline mode, triggers are always
reported before the next instruction begins execution and trigger reporting can be
considered precise.
Ignore pending interrupts.
1 Core ignores any pending interrupt requests signalled while in single-instruction-step
mode.
0 Core services any pending interrupt requests that were signalled while in single-step
mode.
Single-step mode. Setting SSM puts the processor in single-step mode.
0 Normal mode.
1 Single-step mode. The processor halts after execution of each instruction. While halted,
Reserved, should be cleared.
no overlap. This adds at least 5 cycles to the execution time of each instruction. Given
an average execution latency of 1.6 cycles/instruction, throughput in non-pipeline mode
would be 6.6 cycles/instruction, approximately 25% or less of pipelined performance.
any BDM command can be executed. On receipt of the
executes the next instruction and halts again. This process continues until SSM is
cleared.
Section 30.3.1, “Begin Execution of Taken Branch (PST =
MCF5271 Reference Manual, Rev. 2
Table
Mode.”
30-2.
Description
GO
command, the processor
0x5).”
Memory Map/Register Definition
30-11