MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 14

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

14.1.2
14.2
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.3.4.1
14.3.5
14.4
14.4.1
14.4.2
14.4.3
14.4.3.1
14.4.3.2
14.4.4
14.4.4.1
14.4.4.2
14.4.4.3
14.4.5
15.1
15.2
15.3
15.4
15.4.1
15.4.1.1
15.4.1.2
15.4.1.3
15.4.1.4
15.4.1.5
15.4.1.6
16.1
xiv
Paragraph
Number
DMA Transfer Overview.............................................................................................. 14-4
Memory Map/Register Definition ................................................................................ 14-5
Functional Description................................................................................................ 14-13
Introduction................................................................................................................... 15-1
Low-Power Mode Operation ........................................................................................ 15-1
Interrupt/General-Purpose I/O Pin Descriptions........................................................... 15-2
Memory Map/Register Definition ................................................................................ 15-2
Introduction................................................................................................................... 16-1
Features..................................................................................................................... 14-3
DMA Request Control (DMAREQC) ...................................................................... 14-6
Source Address Registers (SAR0–SAR3) ................................................................ 14-7
Destination Address Registers (DAR0–DAR3) ....................................................... 14-8
Byte Count Registers (BCR0–BCR3) and DMA Status Registers (DSR0–DSR3) . 14-8
DMA Control Registers (DCR0–DCR3)................................................................ 14-10
Transfer Requests (Cycle-Steal and Continuous Modes) ....................................... 14-14
Dual-Address Data Transfer Mode......................................................................... 14-14
Channel Initialization and Startup .......................................................................... 14-15
Data Transfer .......................................................................................................... 14-16
Termination............................................................................................................. 14-20
Register Description ................................................................................................. 15-3
DMA Status Registers (DSR0–DSR3) ................................................................. 14-9
Channel Prioritization......................................................................................... 14-15
Programming the DMA Controller Module ....................................................... 14-15
External Request and Acknowledge Operation.................................................. 14-16
Auto-Alignment.................................................................................................. 14-19
Bandwidth Control.............................................................................................. 14-20
EPORT Pin Assignment Register (EPPAR)......................................................... 15-3
EPORT Data Direction Register (EPDDR).......................................................... 15-4
Edge Port Interrupt Enable Register (EPIER) ...................................................... 15-5
Edge Port Data Register (EPDR).......................................................................... 15-5
Edge Port Pin Data Register (EPPDR) ................................................................. 15-6
Edge Port Flag Register (EPFR)........................................................................... 15-6
Edge Port Module (EPORT)
MCF5271 Reference Manual, Rev. 2
Chip Select Module
Contents
Chapter 15
Chapter 16
Title
Freescale Semiconductor
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