MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 455

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

24.4
This section describes operation of the clock source generator, transmitter, and receiver.
24.4.1
The internal bus clock serves as the basic timing reference for the clock source generator logic,
which consists of a clock generator and a programmable 16-bit divider dedicated to each UART.
The clock generator might not produce standard baud rates if the internal bus clock is used, so
enable the 16-bit divider.
24.4.1.1 Programmable Divider
As
The choice of DTIN or internal bus clock is programmed in the UCSR.
Freescale Semiconductor
Figure 24-17
• An external clock signal on the DTnIN pin. When not divided, DTnIN provides a
• The internal bus clock supplies an asynchronous clock source that is divided by 32 and then
synchronous clock mode; when divided by 16, it is asynchronous.
divided by the 16-bit value programmed in UBG1n and UBG2n. See
“UART Baud Rate Generator Registers
Bits
7–1
0
Figure 24-16. UART Output Port Command Registers (UOP1n/UOP0n)
Functional Description
Transmitter/Receiver Clock Source
Name
shows, the UARTn transmitter and receiver can use the following clock sources:
RTS
Address
—
Reset
W
R
Table 24-12. UOP1/UOP0 Field Descriptions
Reserved, should be cleared.
Output port output. Controls assertion (UOP1)/negation (UOP0) of UnRTS output.
0 Not affected.
1 Asserts UnRTS in UOP1. Negates UnRTS in UOP0.
0
0
7
UART0: IPSBAR + 0x0238 (UOP1), IPSBAR + 0x023C (UOP0)
UART1: IPSBAR + 0x0278 (UOP1), IPSBAR + 0x027C (UOP0)
UART2: IPSBAR + 0x02B8 (UOP1) IPSBAR + 0x02BC (UOP0)
MCF5271 Reference Manual, Rev. 2
0
0
6
0
0
5
(UBG1n/UBG2n).”
0
0
4
Description
0
0
3
2
0
0
0
0
1
RTS
0
0
Section 24.3.11,
Functional Description
24-17