MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 82

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
3.7.13 Fault-on-Fault Halt
If a ColdFire processor encounters any type of fault during the exception processing of another
fault, the processor immediately halts execution with the catastrophic “fault-on-fault” condition.
A reset is required to force the processor to exit this halted state.
3.7.14 Reset Exception
Asserting the reset input signal to the processor causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from
catastrophic failure. Reset also aborts any processing in progress when the reset input is
recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the S-bit and disables
tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets the processor’s
interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero
(0x00000000). The control registers specifying the operation of any memories (e.g., cache and/or
RAM modules) connected directly to the processor are disabled.
Once the processor is granted the bus, it then performs two longword read bus cycles. The first
longword at address 0 is loaded into the stack pointer and the second longword at address 4 is
loaded into the program counter. After the initial instruction is fetched from memory, program
execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault halted state.
ColdFire processors load hardware configuration information into the D0 and D1 general-purpose
registers after system reset. The hardware configuration information is loaded immediately after
the reset-in signal is negated. This allows an emulator to read out the contents of these registers
via BDM to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in
3-16
Other implementation-specific supervisor registers are also affected.
Refer to each of the modules in this user’s manual for details on these
registers.
MCF5271 Reference Manual, Rev. 2
NOTE
Freescale Semiconductor
Figure
3-6.