MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 486

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

I
25.5.5 I
In master-receive mode, reading the I2DR allows a read to occur and initiates next the byte data
to be received. In slave mode, the same function is available once the I
address.
25-12
2
C Interface
Bits
2
1
0
2
C Data I/O Register (I2DR)
Name
RXAK
SRW
Address
IIF
Reset
W
Table 25-5. I2SR Field Descriptions (Continued)
R
Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of
the calling address sent from the master. SRW is valid only when a complete transfer has
occurred, no other transfers have been initiated, and the I
address match.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
I
0 No I
1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set
Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle.
0 An acknowledge signal was received after the completion of 8-bit data transmission on
1 No acknowledge signal was detected at the ninth clock.
2
• Complete one byte transfer (set at the falling edge of the ninth clock)
• Reception of a calling address that matches its own specific address in slave-receive
• Arbitration lost
C interrupt. Must be cleared by software by writing a zero in the interrupt routine.
Figure 25-13. I
when one of the following occurs:
mode
the bus
0
7
2
C interrupt pending
MCF5271 Reference Manual, Rev. 2
0
6
0
5
2
C Data I/O Register (I2DR)
IPSBAR + 0x00_0310
0
4
Data
Description
0
3
2
0
2
C module is a slave and has an
0
1
2
C has received its slave
0
0
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