MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 619

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

M
MAC, see EMAC
MDHA
Memory map
Freescale Semiconductor
wait 8-5
logic 26-14
memory map 26-3
modes 26-2
operation
registers
CCM 9-3
chip select module 16-6
clock module 7-8
debug 30-5
EMAC 4-6
EPORT 15-2
Ethernet 19-6
GPIO 12-9
I
interrupt controller 13-4
JTAG 29-5
MDHA 26-3
PIT 21-2
power management 8-1
QSPI 23-9
reset controller 10-2
RNG 27-1
SCM 11-2
SDRAM controller 18-5
SKHA 28-6
timers
UART modules 24-4
2
C 25-8
HASH 26-15
HMAC 26-15
IPAD 26-16
MAC 26-18
NMAC 26-19
OPAD 26-16
SHA-1 EHMAC 26-17
command (MDCMR) 26-7
control (MDCR) 26-6
data size (MDDSR) 26-11
error status (MDESR) 26-10
input FIFO (MDIF) 26-12
message data size (MDMDS) 26-12
message digest registers 0 (MDDx0) 26-12
message digest registers 1 (MDDx1) 26-13
mode (MDMR) 26-4
status (MDSR) 26-8
DTIM 22-3
WDT 20-2
MCF5271 Reference Manual, Rev. 2
P
PLL
Power management
Program counter 3-3
charge pump/loop filter 7-22
lock detection 7-23
loss-of-clock
loss-of-lock
multiplication factor divider (MFD) 7-23
operation 7-21
phase and frequency detector (PFD) 7-22
voltage control output (VCO) 7-23
low-power modes 8-4
memory map 8-1
registers
alternate clock selection 7-25
detection 7-25
reset 7-25
stop mode 7-26
conditions 7-24
reset 7-25
normal mode 7-5
doze 8-5
peripheral behavior
run 8-5
stop 8-5
summary 8-11
wait 8-5
low-power control (LPCR) 8-3
low-power interrupt control (LPICR) 8-2
CCM 8-9
chip select module 8-7
clock module 8-10
core 8-6
debug 8-10
DMA controller 8-7
DTIM 8-8
EPORT 8-10
Ethernet 8-9
GPIO 8-9
I
interrupt controller 8-8
JTAG 8-11
PIT 8-10
QSPI 8-8
reset controller 8-9
SCM 8-6
SDRAM controller 8-6
SRAM 8-6
UART modules 8-7
WDT 8-10
2
C 8-7
,
7-23
Index-5