MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 43

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

1.3.2
The processor core is comprised of two separate pipelines that are decoupled by an instruction
buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address
generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that
holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The
OEP includes two pipeline stages. The first stage decodes instructions and selects operands
(DSOC); the second stage (AGEX) performs instruction execution and calculates operand
effective addresses, if needed.
The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support
for a separate user stack pointer register and four new instructions to assist in bit processing.
Additionally, the MCF5271 core includes the enhanced multiply-accumulate unit (EMAC) for
improved signal processing capabilities. The EMAC implements a 4-stage execution pipeline,
optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. Supported
operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands
and a complete set of instructions to process these data types. The EMAC provides superb support
for execution of DSP operations within the context of a single processor at a minimal hardware
cost.
Freescale Semiconductor
• Chip Integration Module (CIM)
• General Purpose I/O interface
• JTAG support for system level board testing
— Byte/write enables (byte strobes)
— Ability to boot from external memories that are 8,16, or 32 bits wide
— System configuration during reset
— Selects one of four clock modes
— Sets boot device and its data port width
— Configures output pad drive strength
— Unique part identification number and part revision number
— Reset
— Up to 142 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Unused peripheral pins may be used as extra GPIO
– Separate reset in and reset out signals
– Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss
– Status flag indication of source of last reset
V2 Core Overview
of clock, PLL loss of lock
MCF5271 Reference Manual, Rev. 2
Features
1-7