MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 238

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

General Purpose I/O Module
12.3.1.5.5 SDRAM Control Pin Assignment Register (PAR_SDRAM)
The PAR_SDRAM register controls the function of the SDRAM controller pins.
12-22
Bits
7–4
3–2
1
0
Address
Figure 12-33. Chip Select Pin Assignment Register (PAR_CS)
Figure 12-34. SDRAM Control Pin Assignment (PAR_SDRAM)
PAR_CS
Reset
Name
Address
—
W
Reset
R PAR_CSSDCS
W
R
0
7
CS[7:4] pin assignment. The PAR_CS[7:4] bits configure the CS[7:4] pins for their primary
functions or GPIO.
0 CS[7:4] pins configured for GPIO
1 CS[7:4] pins configured for EIM CS[7:4] function
CS[3:2] Pin Assignment Bit. The PAR_CS[3:2] bits configure the CS[3:2] pins for their
primary functions or GPIO.
0 CS[3:2] pins configured for GPIO
1 CS[3:2] pins configured for EIM CS[3:2] or SD_CS[1:0] function
Note: The selection between the EIM chip select function and SDRAMC chip select
function on each of the CS[3:2] pins is determined by the value of the PAR_SDRAM[7:6]
bits. See
for more details on the PAR_SDRAM bits.
CS1 Pin Assignment Bit. The PAR_CS1 bit configures the CS1 pin for its primary function
or GPIO.
0 CS1 pin configured for GPIO
1 CS1 pin configured for EIM CS1 function
Reserved, should be cleared.
Table 12-12. PAR_CS Field Descriptions
1
7
0
6
Section 12.3.1.5.5, “SDRAM Control Pin Assignment Register
MCF5271 Reference Manual, Rev. 2
1
6
SDWE
PAR_
1
5
1
5
IPSBAR + 0x10_0045
IPSBAR + 0x10_0046
PAR_CS
SCAS
PAR_
1
4
1
4
Description
SRAS
PAR_
1
3
1
3
2
1
SCKE
PAR_
2
1
1
1
PAR_SDCS
1
1
0
0
0
Freescale Semiconductor
1
0
(PAR_SDRAM),”