MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 40

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Overview
1.3
1.3.1
1-4
• Version 2 ColdFire variable-length RISC processor core
• System debug support
• On-chip memories
• Fast Ethernet Controller (FEC)
• Three Universal Asynchronous Receiver Transmitters (UARTs)
— Static operation
— 32-bit address and data path on-chip
— Processor core runs at twice the internal bus frequency
— Sixteen general-purpose 32-bit data and address registers
— Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support
— Illegal instruction decode that allows for 68K emulation support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with two user-visible hardware breakpoint registers (PC and
— 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus
— 10 BaseT capability, half duplex or full duplex
— 100 BaseT capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
— Media independent interface (MII) to external transceiver (PHY)
— 16-bit divider for clock generation
— Interrupt control logic
— Maskable interrupts
Features
Feature Overview
support the user stack pointer register, and 4 new instructions for improved bit
processing
32-bit signal processing algorithms
address with optional data) that can be configured into a 1- or 2-level trigger
masters (e.g., DMA, FEC)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor