MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 424

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Queued Serial Peripheral Interface (QSPI) Module
The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation,
the following sequence repeats:
Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed.
After each command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a
match occurs, QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting
QWR[WREN] enables wraparound mode.
QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0
unless another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but
is changed to show the last queue entry before the QSPI is enabled. QWR[NEWQP] and
QWR[ENDQP] can be written at any time. When the QWR[NEWQP] value changes, the internal
pointer value also changes unless a transfer is in progress, in which case the transfer completes
normally. Leaving QWR[NEWQP] and QWR[ENDQP] set to 0x0 causes a single transfer to occur
when the QSPI is enabled.
Data is transferred relative to QSPI_CLK which can be generated in any one of four combinations
of phase and polarity using QMR[CPHA,CPOL]. Data is transferred with the most significant bit
(msb) first. The number of bits transferred defaults to 8, but can be set to any value between 8 and
16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]).
23.2.1 QSPI RAM
The QSPI contains an 80-Byte block of static RAM that can be accessed by both the user and the
QSPI. This RAM does not appear in the device memory map because it can only be accessed by
the user indirectly through the QSPI address register (QAR) and the QSPI data register (QDR).
The RAM is divided into three segments with 16 addresses each:
The transmit and command RAM are user write-only. The receive RAM is user read-only.
Figure 23-2
reset.
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48
separate locations that comprise 16 words of transmit data, 16 words of receive data and 16 bytes
of commands.
23-4
1. The command pointed to by the internal pointer is executed.
2. The value in the internal pointer is copied into QWR[CPTQP].
3. The internal pointer is incremented.
• Receive data RAM, the initial destination for all incoming data
• Transmit data RAM, a buffer for all out-bound data
• Command RAM, where commands are loaded
shows the RAM configuration. The RAM contents are undefined immediately after a
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor