MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 543

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

29.2.6 Test Data Output/Development Serial Output (TDO/DSO)
The TDO pin is the lsb-first data output. Data is clocked out of TDO on the falling edge of TCLK.
TDO is tri-stateable and is actively driven in the shift-IR and shift-DR controller states.
The DSO pin provides serial output data in BDM mode.
29.3 Memory Map/Register Definition
The JTAG module registers are not memory mapped and are only accessible through the
TDO/DSO pin.
29.3.1 Register Descriptions
All registers are shift-in and parallel load.
29.3.1.1 Instruction Shift Register (IR)
The JTAG module uses a -bit shift register with no parity. The IR transfers its value to a parallel
hold register and applies an instruction on the falling edge of TCLK when the TAP state machine
is in the update-IR state. To load an instruction into the shift portion of the IR, place the serial data
on the TDI pin before each rising edge of TCLK. The msb of the IR is the bit closest to the TDI
pin, and the lsb is the bit closest to the TDO pin.
29.3.1.2 IDCODE Register
The IDCODE is a read-only register; its value is chip dependent. For more information, see
Section 29.4.3.2, “IDCODE
Freescale Semiconductor
Reset
Reset
W
W
R
R
31
15
30
14
PRN
PRN
PIN
PIN
29
13
28
12
Instruction.”
Figure 29-2. IDCODE Register
27
11
0
0
MCF5271 Reference Manual, Rev. 2
26
10
1
0
25
1
0
9
DC
24
1
0
8
23
0
0
7
JEDEC
22
1
6
0
21
0
5
20
1
4
Memory Map/Register Definition
19
1
3
PIN
PIN
18
1
2
17
0
1
16
ID
1
0
29-5