MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 445

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

24.3.2
The UMR2n registers control UART module configuration. UMR2n can be read or written when
the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses
do not update the pointer.
Freescale Semiconductor
Bits
7–6
5
UART Mode Register 2 (UMR2n)
TxRTS
Name
CM
Address
Reset
W
Channel mode. Selects a channel mode.
modes.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
Transmitter ready-to-send. Controls negation of UnRTS to automatically terminate a message
transmission. Attempting to program a receiver and transmitter in the same channel for UnRTS
control is not permitted and disables UnRTS control for both.
0 The transmitter has no effect on UnRTS.
1 In applications where the transmitter is disabled after transmission completes, setting this bit
R
Figure 24-4. UART Mode Register 2 (UMR2n)
automatically clears UOP[RTS] one bit time after any characters in the channel transmitter
shift and holding registers are completely sent, including the programmed number of stop bits.
0
7
Table 24-4. UMR2n Field Descriptions
After UMR1n is read or written, the pointer points to UMR2n.
CM
IPSBAR + 0x0200 (UART0); IPSBAR + 0x0240 (UART1);
MCF5271 Reference Manual, Rev. 2
0
6
TXRTS TXCTS
0
5
IPSBAR + 0x0280 (UART2)
0
4
Section 24.4.3, “Looping
Description
0
3
2
0
SB
0
1
Modes,” describes individual
Memory Map/Register Definition
0
0
24-7