MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 63

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

2.3.12 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the
BDM logic.
Freescale Semiconductor
DMA Timer 0 Input
DMA Timer 0 Output
DMA Timer 1 Input
DMA Timer 1 Output
DMA Timer 2 Input
DMA Timer 2 Output
DMA Timer 3 Input
DMA Timer 3 Output
Test Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Development Serial
Clock
Breakpoint
Development Serial
Input
Signal Name
Signal Name
DT0IN
DT0OUT
DT1IN
DT1OUT
DT2IN
DT2OUT
DT3IN
DT3OUT
TRST
TCLK
TMS
TDI
TDO
DSCLK
BKPT
DSI
Abbreviation
Abbreviation
Table 2-13. Debug Support Signals
Table 2-12. DMA Timer Signals
MCF5271 Reference Manual, Rev. 2
Can be programmed to cause events to occur in first platform timer. It
can either clock the event counter or provide a trigger to the timer
value capture logic.
The output from first platform timer.
Can be programmed to cause events to occur in the second platform
timer. This can either clock the event counter or provide a trigger to
the timer value capture logic.
The output from the second platform timer.
Can be programmed to cause events to occur in the third platform
timer. It can either clock the event counter or provide a trigger to the
timer value capture logic.
The output from the third platform timer.
Can be programmed as an input that causes events to occur in the
fourth platform timer. This can either clock the event counter or
provide a trigger to the timer value capture logic.
The output from the fourth platform timer.
This active-low signal is used to initialize the JTAG logic
asynchronously.
Used to synchronize the JTAG logic.
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
Serial input for test instructions and data. TDI is sampled on the
rising edge of TCLK.
Serial output for test instructions and data. TDO is three-stateable
and is actively driven in the shift-IR and shift-DR controller states.
TDO changes on the falling edge of TCLK.
Clocks the serial communication port to the BDM module during
packet transfers.
Used to request a manual breakpoint.
This internally-synchronized signal provides data input for the serial
communication port to the BDM module.
Function
Function
Signal Primary Functions
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
2-13