MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 450

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

UART Modules
24.3.6
The receive buffers (shown in
holding registers, which act as a FIFO. UnRXD is connected to the serial shift register. The CPU
reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift
register is full (see
24.3.7
The transmit buffers consist of the transmitter holding register and the transmitter shift register.
The holding register accepts characters from the bus master if channel’s USRn[TxRDY] is set. A
write to the transmit buffer clears USRn[TxRDY], inhibiting any more characters until the shift
register can accept more data. When the shift register is empty, it checks if the holding register has
a valid character to be sent (TxRDY = 0). If there is a valid character, the shift register loads it and
sets USRn[TxRDY] again. Writes to the transmit buffer when the channel’s TxRDY = 0 and when
the transmitter is disabled have no effect on the transmit buffer.
Figure 24-9
24-12
Bits
1–0
Value
00
01
10
11
shows UTBn. TB contains the character in the transmit buffer.
UART Receive Buffers (URBn)
UART Transmit Buffers (UTBn)
NO ACTION TAKEN
RECEIVER ENABLE
RECEIVER DISABLE
Address
Command
Figure
Reset
Table 24-7. UCRn Field Descriptions (Continued)
—
W
R
Figure 24-8. UART Receive Buffer (URBn)
24-18). RB contains the character in the receiver.
1
7
IPSBAR + 0x020C (URB0); IPSBAR + 0x024C (URB1);
Causes the receiver to stay in its current mode. If the receiver is enabled, it
remains enabled; if disabled, it remains disabled.
If the UART module is not in multidrop mode (UMR1n[PM] ≠ 11),
enables the channel's receiver and forces it into search-for-start-bit state. If the
receiver is already enabled, this command has no effect.
Disables the receiver immediately. Any character being received is lost. The
command does not affect receiver status bits or other control registers. If the
UART module is programmed for local loop-back or multidrop mode, the receiver
operates even though this command is selected. If the receiver is already
disabled, the command has no effect.
Reserved, do not use.
Figure
MCF5271 Reference Manual, Rev. 2
1
6
RC (This field selects a single command)
24-8) contain one serial shift register and three receiver
1
5
IPSBAR + 0x028C (URB2)
1
4
RB
1
3
Description
2
1
1
1
1
0
Freescale Semiconductor
RECEIVER ENABLE