MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 21

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

24.4.2.3
24.4.3
24.4.3.1
24.4.3.2
24.4.3.3
24.4.4
24.4.5
24.4.5.1
24.4.5.2
24.4.6
24.4.6.1
24.4.6.2
25.1
25.2
25.3
25.4
25.4.1
25.4.2
25.4.3
25.4.4
25.4.5
25.4.6
25.4.7
25.4.8
25.5
25.5.1
25.5.2
25.5.3
25.5.4
25.5.5
25.6
25.6.1
25.6.2
25.6.3
25.6.4
25.6.5
25.6.6
Freescale Semiconductor
Paragraph
Number
Introduction................................................................................................................... 25-1
Overview....................................................................................................................... 25-1
Features ......................................................................................................................... 25-1
I
Memory Map/Register Definition ................................................................................ 25-8
I
2
2
C System Configuration............................................................................................. 25-3
C Programming Examples ....................................................................................... 25-13
Looping Modes ....................................................................................................... 24-24
Multidrop Mode...................................................................................................... 24-25
Bus Operation ......................................................................................................... 24-27
Programming .......................................................................................................... 24-27
START Signal........................................................................................................... 25-3
Slave Address Transmission..................................................................................... 25-4
Data Transfer ............................................................................................................ 25-4
Acknowlege .............................................................................................................. 25-4
STOP Signal ............................................................................................................. 25-5
Repeated START...................................................................................................... 25-5
Clock Synchronization and Arbitration .................................................................... 25-6
Handshaking and Clock Stretching........................................................................... 25-8
I
I
I
I
I
Initialization Sequence............................................................................................ 25-13
Generation of START............................................................................................. 25-14
Post-Transfer Software Response........................................................................... 25-14
Generation of STOP................................................................................................ 25-15
Generation of Repeated START............................................................................. 25-16
Slave Mode ............................................................................................................. 25-16
2
2
2
2
2
C Address Register (I2ADR) ................................................................................. 25-8
C Frequency Divider Register (I2FDR)................................................................. 25-9
C Control Register (I2CR)................................................................................... 25-10
C Status Register (I2SR)...................................................................................... 25-11
C Data I/O Register (I2DR) ................................................................................. 25-12
FIFO.................................................................................................................... 24-23
Automatic Echo Mode........................................................................................ 24-24
Local Loop-Back Mode...................................................................................... 24-24
Remote Loop-Back Mode................................................................................... 24-25
Read Cycles ........................................................................................................ 24-27
Write Cycles ....................................................................................................... 24-27
Interrupt and DMA Request Initialization.......................................................... 24-28
UART Module Initialization Sequence .............................................................. 24-30
MCF5271 Reference Manual, Rev. 2
Contents
I
2
Chapter 25
C Interface
Title
Number
Page
xxi