MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 379

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.3.2 User Initialization (Prior to Setting ECR[ETHER_EN])
The user needs to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact
values will depend on the particular application. The sequence is not important.
Ethernet MAC registers requiring initialization are defined in
FEC FIFO/DMA registers that require initialization are defined in
Freescale Semiconductor
Table 19-32. FEC User Initialization (Before ECR[ETHER_EN])
Table 19-30. ECR[ETHER_EN] De-Assertion Effect on FEC
Table 19-31. User Initialization (Before ECR[ETHER_EN])
Descriptor Controller block
Register/Machine
RECV block
XMIT block
DMA block
Clear MIB_RAM (locations IPSBAR + 0x1200-0x12FC)
PALR / PAUR (only needed for full duplex flow control)
RDAR
TDAR
OPD (only needed for full duplex flow control)
Initialize (Empty) Transmit Descriptor ring
Initialize (Empty) Receive Descriptor ring
MCF5271 Reference Manual, Rev. 2
Clear EIR (write 0xFFFF_FFFF)
Initialize FRSR (optional)
Initialize EMRBR
TFWR (optional)
MSCR (optional)
Initialize ERDSR
Initialize ETDSR
Initialize EIMR
GAUR / GALR
Description
IALR / IAUR
Description
RCR
TCR
Transmission is aborted (bad CRC
All DMA activity is terminated
Receive activity is aborted
Halt operation
Reset Value
appended)
Cleared
Cleared
Table
Table
19-31.
19-32.
Functional Description
19-35