MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 267

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

14.1.2 Features
The DMA controller module features are as follows:
Freescale Semiconductor
• Four independently programmable DMA controller channels
• Auto-alignment feature for source or destination accesses
• Dual-address transfers
• Channel arbitration on transfer boundaries
Read Data Bus
Throughout this chapter “external request” and DREQ are used to
refer to a DMA request from one of the on-chip UARTS, DMA timers,
or DREQ signals. For details on the connections associated with DMA
request inputs, see
(DMAREQC).”
Data Path
Internal
Bus
Requests
Channel
Write Data Bus
Figure 14-1. DMA Signal Diagram
Channel 0
DREQ0
MCF5271 Reference Manual, Rev. 2
DAR0
BCR0
DCR0
DSR0
SAR0
Data Path
Control
Channel
Enables
Section 14.3.1, “DMA Request Control
Control
Channel 1
DREQ1
MUX
DAR1
BCR1
DCR1
DSR1
SAR1
NOTE
Arbitration/
Control
MUX
Channel 2
Channel
Attributes
DREQ2
DAR2
BCR2
DCR2
DSR2
SAR2
Current Master Attributes
System Bus Address
System Bus Size
Channel 3
DREQ3
DCR3
SAR3
DAR3
BCR3
DSR3
Interrupts
Bus Interface
Bus Signals
Registered
Introduction
14-3