MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 44

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Overview
1.3.3
The ColdFire processor core debug interface is provided to support system debugging in
conjunction with low-cost debug and emulator development tools. Through a standard debug
interface, users can access real-time trace and debug information. This allows the processor and
system to be debugged at full speed without the need for costly in-circuit emulators. The debug
interface is a superset of the BDM interface provided on the 683xx family of parts.
The on-chip breakpoint resources include a total of 8 programmable registers—a set of address
registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit
data mask register), an address attribute register, a trigger definition register, and one 32-bit PC
register plus a 32-bit PC mask register. These registers can be accessed through the dedicated
debug serial communication channel or from the processor’s supervisor mode programming
model. The breakpoint registers can be configured to generate triggers by combining the address,
data, and PC conditions in a variety of single or dual-level definitions. The trigger event can be
programmed to generate a processor halt or initiate a debug interrupt exception.
To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and
debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status,
captured operand data, and branch target addresses defining processor activity at the CPU’s clock
rate.
1.3.4
The MCF5271 supports circuit board test strategies based on the Test Technology Committee of
IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP)
consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass
register, a 330-bit boundary-scan register, and a 32-bit ID register). The boundary scan register
links the device’s pins into one shift register. Test logic, implemented using static logic design, is
independent of the device system logic.
The MCF5271 implementation can do the following:
1-8
• Perform boundary-scan operations to test circuit board electrical continuity
• Sample MCF5271 system pins during operation and transparently shift out the result in the
• Bypass the MCF5271 for a given circuit board test by effectively reducing the
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
boundary scan register
boundary-scan register to a single bit
Integrated Debug Module
JTAG
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor