MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 416

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DMA Timers (DTIM0–DTIM3)
22.2.10 DMA Timer Capture Registers (DTCRn)
Each DTCRn, shown in
operation when an edge occurs on DTINn, as programmed in DTMRn. The system clock is
assumed to be the clock source. DTINn cannot simultaneously function as a clocking source and
as an input capture pin. Indeterminate operation will result if DTINn is set as the clock source
when the input capture mode is used.
22.2.11 DMA Timer Counters (DTCNn)
The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Writing
to DTCNn, shown in
rising edge (system clock ÷ 1, system clock ÷ 16, or DTINn).
22-8
Address
Address
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
31
15
31
15
1
1
0
0
30
14
30
14
1
1
0
0
Figure 22-5. DMA Timer Reference Registers (DTRRn)
Figure 22-6. DMA Timer Capture Registers (DTCRn)
29
13
29
13
Figure
1
1
0
0
Figure
IPSBAR + 0x00_0404 (DTRR0); IPSBAR + 0x00_0444 (DTRR1);
IPSBAR + 0x00_0408 (DTCR0); IPSBAR + 0x00_0448 (DTCR1);
IPSBAR + 0x00_0484 (DTRR2); IPSBAR + 0x00_04C4 (DTRR3)
IPSBAR + 0x00_0488 (DTCR2); IPSBAR + 0x00_04C8 (DTCR3)
28
12
28
12
1
1
0
0
22-7, clears it. The timer counter increments on the clock source
22-6, latches the corresponding DTCNn value during a capture
27
27
11
11
1
1
0
0
MCF5271 Reference Manual, Rev. 2
26
10
26
10
1
1
0
0
CAP (32-bit capture counter value)
CAP (32-bit capture counter value)
25
25
1
1
0
0
9
9
24
24
1
1
0
0
8
8
REF
REF
23
23
1
1
0
0
7
7
22
22
1
6
1
0
6
0
21
21
1
1
0
0
5
5
20
20
1
1
0
0
4
4
19
19
1
1
0
0
3
3
Freescale Semiconductor
18
18
1
1
0
0
2
2
17
17
1
1
0
0
1
1
16
16
1
1
0
0
0
0