MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 84

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
Information loaded into D1 defines the local memory hardware configuration as shown in
Figure
3-18
Table 3-11. D1 Local Memory Hardware Configuration Information Field Description
Reset
Reset
31–30
29–28
27–24
23–16
15–14
Bits
Bits
3-7.
7–4
3–0
Table 3-10. D0 Hardware Configuration Info Field Description (Continued)
W
W
R
R
31
15
0
0
BUSW
CL
DEBUG
BUSW
Name
Name
ICSIZ
ISA
30
14
ICA
0
0
CL
—
29
13
0
0
DCA
ICA
Instruction set architecture (ISA) revision number.
0000 ISA_A
0001 ISA_B
0010 ISA_C
1000 ISA_A+ (ISA_A with the addition of the BYTEREV, BITREV, FF1, and STLDSR
0011-1111 Reserved.
Debug module revision number.
0000 DEBUG_A (This is the value used for MCF5271)
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
0101–1111 Reserved.
Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.
Instruction cache associativity.
00 Four-way.
01 Direct mapped. (This is the value used for MCF5271)
Instruction cache size.
0101 8KB instruction cache. (This is the value used for MCF5271)
All other values do not apply for MCF5271
Reserved for MCF5271
Encoded bus data width.
00 32-bit data bus (only configuration currently in use).
Figure 3-7. D1 Hardware Configuration Info
28
12
1
1
instructions. This is the value used for MCF5271.)
27
11
0
0
MCF5271 Reference Manual, Rev. 2
26
10
1
0
DCSIZ
ICSIZ
25
0
0
9
24
1
0
8
23
Description
Description
0
1
7
RAM1SIZ
22
0
6
0
21
0
0
5
20
0
0
4
—
19
0
0
3
Freescale Semiconductor
ROM1SIZ
18
0
0
2
17
0
0
1
16
0
0
0