MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 507

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

26.3.3.5 Hashing Engine Control
This module is the control unit of the MDHA that is capable of computing the Secure Hash
Algorithm (SHA-1) and Message Digest 5 algorithm (MD5). This module keeps track of all
rounds and tells the rest of the module when the operation has been completed.
26.3.3.6 Status Interrupt
This block generates the error interrupt if the host performs an illegal operation. The cause of the
error is flagged in the MDISR
(MDISR and
core from continuing operation with invalid data.
26.4
26.4.1
26.4.2
The HMAC is done in three separate steps without the MACFULL bit. Each step requires the
reinitialization of the MDHA.
Freescale Semiconductor
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, data padding, and algorithm initialization.
4. Write message data into the FIFO in longwords.
5. MDDSR register write. Load this register with the length of the message data (without
6. Set MDCMR[GO].
7. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful
8. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from
padding) in bytes.
completion (or failure).
the message digest registers.
Initialization/Application Information
Performing a Standard HASH Operation
Performing a HMAC Operation Without the MACFULL Bit
MDIMR)”). If an error occurs, the MDHA core engine is halted. This prevents the
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message
data. This will most likely occur if the MDDSR write is not received
or auto-padding is disabled and a partial message block is provided.
(Section 26.2.5, “MDHA Interrupt Status & Mask Registers
MCF5271 Reference Manual, Rev. 2
NOTE
Initialization/Application Information
26-15