MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 548

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

IEEE 1149.1 Test Access Port (JTAG)
29.4.3.4 ENABLE_TEST_CTRL Instruction
The ENABLE_TEST_CTRL instruction selects a -bit shift register (TEST_CTRL) for connection
as a shift path between the TDI and TDO pin. When the user transitions the TAP controller to the
UPDATE_DR state, the register transfers its value to a parallel hold register.
29.4.3.5 HIGHZ Instruction
The HIGHZ instruction eliminates the need to backdrive the output pins during circuit-board
testing. HIGHZ turns off all output drivers, including the 2-state drivers, and selects the bypass
register. HIGHZ also asserts internal reset for the MCU system logic to force a predictable internal
state.
29.4.3.6 CLAMP Instruction
The CLAMP instruction selects the 1-bit bypass register and asserts internal reset while
simultaneously forcing all output pins and bidirectional pins configured as outputs to the fixed
values that are preloaded and held in the boundary scan update register. CLAMP enhances test
efficiency by reducing the overall shift path to a single bit (the bypass register) while conducting
an EXTEST type of instruction through the boundary scan register.
29.4.3.7 BYPASS Instruction
The BYPASS instruction selects the bypass register, creating a single-bit shift register path from
the TDI pin to the TDO pin. BYPASS enhances test efficiency by reducing the overall shift path
when a device other than the ColdFire processor is the device under test on a board design with
multiple chips on the overall boundary scan chain. The shift register lsb is forced to logic 0 on the
rising edge of TCLK after entry into the capture-DR state. Therefore, the first bit shifted out after
selecting the bypass register is always logic 0. This differentiates parts that support an IDCODE
register from parts that support only the bypass register.
29.5 Initialization/Application Information
29.5.1 Restrictions
The test logic is a static logic design, and TCLK can be stopped in either a high or low state without
loss of data. However, the system clock is not synchronized to TCLK internally. Any mixed
operation using both the test logic and the system functional logic requires external
synchronization.
29-10
data to the update cells. The data is applied to the external output pins by the EXTEST or
CLAMP instruction.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor