MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 397

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

20.2.1.1 Watchdog Control Register (WCR)
The 16-bit WCR configures watchdog timer operation.
Freescale Semiconductor
Address
• Watchdog service register (WSR), which requires a service sequence to
Reset
15–4
prevent reset
Bits
W
R
3
2
1
0
15
0
0
HALTED
14
0
0
Name
DOZE
WAIT
EN
—
13
0
0
Figure 20-2. Watchdog Control Register (WCR)
Reserved, should be cleared.
Wait mode bit. Controls the function of the watchdog timer in wait mode. Once written, the
WAIT bit is not affected by further writes except in halted mode. Reset sets WAIT.
0 Watchdog timer not affected in wait mode
1 Watchdog timer stopped in wait mode
Doze mode bit. Controls the function of the watchdog timer in doze mode. Once written,
the DOZE bit is not affected by further writes except in halted mode. Reset sets DOZE.
0 Watchdog timer not affected in doze mode
1 Watchdog timer stopped in doze mode
Halted mode bit. Controls the function of the watchdog timer in halted mode. Once written,
the HALTED bit is not affected by further writes except in halted mode.
During halted mode, watchdog timer registers can be written and read normally. When
halted mode is exited, timer operation continues from the state it was in before entering
halted mode, but any updates made in halted mode remain. If a write-once register is
written for the first time in halted mode, the register is still writable when halted mode is
exited.
0 Watchdog timer not affected in halted mode
1 Watchdog timer stopped in halted mode
Note: Changing the HALTED bit from 1 to 0 during halted mode starts the watchdog timer.
Changing the HALTED bit from 0 to 1 during halted mode stops the watchdog timer.
Watchdog enable bit. Enables the watchdog timer. Once written, the EN bit is not affected
by further writes except in halted mode. When the watchdog timer is disabled, the
watchdog counter and prescaler counter are held in a stopped state.
0 Watchdog timer disabled
1 Watchdog timer enabled
12
0
0
Table 20-3. WCR Field Descriptions
11
0
0
MCF5271 Reference Manual, Rev. 2
10
0
0
0
0
9
IPSBAR + 0x14_0000
8
0
0
0
0
7
Description
0
0
6
0
0
5
0
0
4
WAIT DOZE HALTED EN
Memory Map/Register Definition
1
3
1
2
1
1
1
0
20-3